1. Field of the Invention
The present invention generally relates to an electrostatic discharge protection technique applied to integrated circuitry. More particular, the present invention relates to an electrostatic discharge protection circuit triggered by a diode.
2. Description of the Related Art
Electrostatic discharge, ESD hereinafter, may occur at any time during the phases of testing, assembly, installation, operation, etc., and cause damage to integrated circuits (ICs). Nowadays, the protection of the integrated circuits from ESD damage has become a concern for IC designers. However, sub-micron CMOS ICs have become increasingly vulnerable to ESD damage due to advanced processes, such as the use of lightly-doped drain structures and clad silicide diffusions. Conventionally, lateral semiconductor-controlled rectifiers (LSCRs), for example, disclosed in U.S. Pat. No. 5,012,317, have been employed as ESD protection circuits for shunting ESD stress. A cross-sectional view of the conventional LSCR is illustrated in FIG. 1.
Referring to FIG. 1, the LSCR is fabricated onto a P-type semiconductor substrate 10, for example a silicon substrate, in a predetermined portion of which an N-well region 11 is formed. A P-type doped region 12 and an N-type doped region 13 are formed within the extent of the N-well region 11 and spaced apart from each other. An N-type doped region 14 and a P-type doped region 15 are formed within the extent of the P-type semiconductor substrate 10 and spaced apart from each other, where the M-type doped region 14 is closer to the N-well region 11 than the P-type doped region 15.
In the drawing, the P-type doped region 12 and the N-type doped region 13 are together connected to an IC pad 1. The IC pad 1 is an input pad, output pad, I/O pad or power pad for an internal circuit 2, which is vulnerable to ESD damage and should be protected by the LSCR. In addition, the N-type doped region 14 and the P-type doped region 15 are together connected to a power node Vss. Generally, the power node is connected to a ground under normal operation.
Correspondingly, the P-type doped region 12, the N-well region 11, and the P-type semiconductor substrate 10 serve as the emitter, base, and collector, respectively, of a PNP bipolar junction transistor 20. The N-well region 11, the P-type semiconductor substrate 10, and the N-type doped region 14 serve as the collector, base, and emitter, respectively, of an NPN bipolar junction transistor 21. Referring to FIG. 2, the equivalent circuit diagram of the conventional LSCR as shown in FIG. 1 is schematically illustrated. In the drawing, resistors 22 and 23 designate the respective spreading resistance of the N-well region 11 and the P-type semiconductor substrate 10.
However, the triggering of the conventional SCR to activate and thus bypass the ESD stress relies heavily on the P/N junction breakdown between the semiconductor substrate 10 and the N-well region 11. Due to the fact that both the substrate and well region are generally doped or implanted with a low doping concentration, the trigger voltage of the LSCR can be up to 30V or more, at which point the ICs may have been adversely affected. Particularly, the LSCR is more reluctant to be triggered when applied to epi-wafer processes.
Therefore, it is an object of the present invention to provide an ESD protection circuit having a semiconductor-controlled rectifier with a floating anode gate. The semiconductor-controlled rectifier can be triggered by means of a diode at a reduced trigger voltage.
It is another object of the present invention to provide an ESD protection circuit having a semiconductor-controlled rectifier with a floating anode gate. The semiconductor-controlled rectifier can clamp the potential of a circuit node to be protected at a low holding voltage.
To achieve the aforementioned objects, the present invention provides an ESD protection circuit having at least one semiconductor-controlled rectifier and a diode. The SCR having a floating anode gate is connected between a first circuit node and a second circuit node. The diode is connected between an anode and a cathode gate of the SCR to activate the SCR so that a potential between the first circuit node and second circuit node can be clamped at about a holding voltage of the SCR during an ESD event.
Accordingly, the trigger voltage of the ESD protection circuit can be reduced to about the breakdown voltage of the diode. Moreover, due to the fact that the semiconductor-controlled rectifier has its anode gate floating, the holding voltage can be further reduced. Therefore, the potential between two circuit nodes can be soon clamped to a quite low holding voltage during an ESD event. Thus, the ESD protection circuit of the present invention has a low trigger voltage as well as a low holding voltage, and can therefore efficiently protect an internal circuit from ESD damage, especially in deep sub-micron process applications.